1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the design of Built-In Self-Test (BIST) circuits for testing components of a microcircuit design.
2. Description of the Related Art
Built-in self-test (BIST) is a technique that allows integrated circuits to test their own operation functionally and/or parametrically. Like other Design-for-Test (DFT) techniques, it makes difficult-to-test circuits easier to test by adding test circuitry to a microcircuit design for such things as test pattern generation, timing analysis, mode selection, and go-/no-go diagnostic tests. BIST includes control circuits to initiate tests and to collect and report the results, even externally to the chip.
BIST circuits often connect to scan logic. Scan logic is another DFT technique that facilitates testing of a microcircuit chip by, for example, replacing traditional sequential elements, such as flip flops, with scannable sequential elements, called scan cells. A scan cell is a traditional latch or flip-flop with an additional input called the scan input and an additional output called the scan output. The portion of the scan cell that comprises the traditional latch or flip-flop remains part of the functional core logic. The scan output of one scan cell, however, connects to the scan input of the next scan cell to form a scan chain. The scan chain allows test patterns to be serially injected into the core logic so that they appear at the outputs of the latches, or flops. Testing is accomplished by shifting test patterns into the scan chains, cycling the system clock one or more times, and capturing the test results within the latches or flops. The results may then be shifted out through the scan chain for analysis by external test equipment or internal BIST logic.
BIST circuits also typically connect to boundary-scan elements. Boundary-Scan (also known as the Joint Test Action Group (JTAG) standard, or IEEE 1149.1) adds boundary-scan cells to each pin on a microcircuit device so that test and control data can be injected into the microcircuit device, tests initiated, and the results shifted out, even when the microcircuit is encased in a package. Boundary-scan test circuits are frequently used to initiate BIST and to report BIST results through, for example, a JTAG interface.
BIST logic does not come without a cost, however. The logic added to a microcircuit design for BIST testing typically intrudes into the critical timing paths of functional signals. BIST logic typically causes functional signals to propagate through additional gates that couple BIST test data onto the functional data paths, reducing the maximum speed of the microcircuit's operation and increasing its power consumption. While BIST makes device testing more efficient, it typically degrades device performance.